1. Field of the Invention
The present invention relates to the field of semiconductor manufacture, and particularly to a phase change memory and a method for fabricating the same.
2. Background of the Invention
Nowadays, a phase change RAM is put forward as a new nonvolatile memory for new type memory application. As for the phase change memory, a storage unit is formed with phase change material for serving as data storage medium. Heat is supplied for phase change of phase change material. According to the supplied heat, the phase change material has two stable phases, for example non-crystal phase and crystal phase. Typical phase change material comprises Ge—Sb—Te (GST), a composition of Ge, Sb and Te, and the like.
When the phase change material is heated at the proximity of melted temperature for a short time and then is cooled rapidly, it may phase change from crystal phase to non-crystal phase. Reversely, when the phase change material is heated below the melted temperature for a long time and then is cooled slowly, it may phase change from non-crystal phase to crystal phase. The phase change material under the non-crystal phase has higher resistance ratio than under the crystal phase. Thus, it can be determined by current through phase change material, that the data stored in the storage unit of the phase change memory is logic “1” (non-crystal phase and high resistance ratio) or logic “0” (crystal phase and low resistance ratio).
In prior art, the phase change memory is LED driven, in which LED and phase change material are both deposited in a vertical insulated material hole. By the virtue of the robust drive ability of the LED, size of the devices and cross-talk between devices is minimized at most, and stability of the phase change is enhanced.
As shown in FIG. 1, a vertical LED driven phase change memory comprises a storage region 10 and a peripheral circuit region 20.
The storage region 10 comprises a storage substrate 11, an N-type ion buried layer 12 on the storage substrate 11, a storage monocrystalline layer 17 on the N-type ion buried layer 12, storage shallow trench isolation (STI) units 13 in the storage monocrystalline layer 17, vertical LEDs and phase change layers 16 on the vertical LEDs. Each storage shallow trench isolation (STI) unit 13 has thickness identical to that of the storage monocrystalline layer 17. The vertical LED comprises an N-type conductive region 14 in the storage monocrystalline layer 17 and between the storage shallow trench isolation (STI) units 13, and a P-type conductive region 15 on the N-type conductive region 14. The vertical LED has thickness identical to that of the storage monocrystalline layer 17.
The peripheral circuit region 20 comprises a peripheral substrate 21, a peripheral monocrystalline layer 25 on the peripheral substrate 21, peripheral shallow trench isolation (STI) units 23 in the monocrystalline layer 25, MOS transistors 24 in the peripheral monocrystalline layer 25 and between the peripheral shallow trench isolation (STI) units 23. Thickness of the peripheral substrate 21 is equal to a sum of that of the N-type ion buried layer 12 and that of the storage substrate 11. The peripheral shallow trench isolation (STI) units 23 have thickness identical to that of the peripheral monocrystalline layer 25.
FIGS. 2-7 are cross-sectional views of intermediate structures of a vertical LED driven phase change memory, illustrating a conventional method for forming the vertical LED driven phase change memory.
Referring to FIG. 2, a substrate is provided, which comprises at least a storage substrate 11 and a peripheral substrate 21.
Referring to FIG. 3, ions (for example arsenic ions) are implanted into the storage substrate 11 to form an N-type ion buried layer 12.
Referring to FIG. 4, the storage monocrystalline layer 17 grows on the N-type ion buried layer 12 by non-selective extensive process. The peripheral monocrystalline layer 25 grows on the peripheral substrate 21 by non-selective extensive process.
Referring to FIG. 5, the storage STI units 13 are formed in the storage monocrystalline layer 17 in such as way that each storage shallow trench isolation (STI) unit 13 has thickness identical to that of the storage monocrystalline layer 17. The peripheral STI units 23 are formed in the peripheral monocrystalline layer 25 in such a way that the peripheral shallow trench isolation (STI) units 23 have thickness identical to that of the peripheral monocrystalline layer 25.
Referring to FIG. 6, the vertical LEDs are formed in the storage monocrystalline layer 17 and between the storage shallow trench isolation (STI) units 13. Each vertical LED comprises an N-type conductive region 14 and a P-type conductive region 15. During the process of formation, N-type ions are implanted into a lower part of the storage monocrystalline layer 17 to form the N-type conductive region 14, and P-type ions are implanted into an upper part of the storage monocrystalline layer 17 to form the P-type conductive region 15 on the N-type conductive region 14. Each vertical LED has an N-type conductive region 14 and a P-type conductive region 15. Thickness of the vertical LED is identical to that of the storage monocrystalline layer 17.
Referring to FIG. 7, phase change layers 16 are formed on the P-type conductive region 15. The MOS transistors 24 are formed in the peripheral monocrystalline layer 25. Finally, a storage region 10 and a peripheral circuit region 20 are completed.
In practical application, the peripheral circuit region 20 may not work. Furthermore, a phase change memory requires high density and low energy consumption. It is desired to reduce drain current of the vertical LEDs and raise the current efficiency of the vertical LEDs. However, in prior art, the vertical LEDs have silicon-based PN junction, carrier drain current formed by electrical field may occur at the PN junction.